Power MOSFETs have typically been developed for applications requiring power switching and power amplification. For power switching applications, the commercially available devices are typically double diffused MOSFETs (DMOSFETs). In a typical transistor, much of the breakdown voltage BV is supported by a drift region, which is lowly doped in order to provide a higher breakdown voltage BV. However, the lowly doped drift region also produces high on-resistance Rds-on. For a typical transistor, Rds-on is proportional to BV2.5. Rds-on therefore increases dramatically with increase in breakdown voltage BV for a conventional transistor.
Superjunctions are a well known type of semiconductor device. Superjunction transistors provide a way to achieve low on-resistance (Rds-on) while maintaining a high off-state breakdown voltage (BV). Vertical superjunction devices include alternating P-type and N-type doped columns formed in the drift region. In the OFF-state of the MOSFET, the columns completely deplete at relatively low voltage and thus can sustain a high breakdown voltage (the columns deplete laterally, so that the entire p and n columns are depleted). For a superjunction, the on-resistance Rds-on increases in direct proportion to the breakdown voltage BV, which is a much less dramatic increase than in the conventional semiconductor structure. A superjunction device may therefore have significantly lower Rds-on than a conventional MOSFET device for the same high breakdown voltage (BV) (or conversely may have a significantly higher BV than a conventional MOSFET for a given Rds-on).
U.S. Pat. No. 4,754,310 discloses a semiconductor device, such as a diode or transistor, that comprises a semiconductor body having a depletion layer formed throughout a portion in at least a high voltage mode of operation of the device, such as, by reverse biasing a rectifying junction. The depleted body portion comprising an interleaved structure of first and second regions of alternating conductivity types carries the high voltage which occurs across the depleted body portion. The thickness and doping concentration of each of these first and second regions are such that when depleted the space charge per unit area formed in each of these regions is balanced at least to the extent that an electric field resulting from any imbalance is less than the critical field strength at which avalanche breakdown would occur in the body portion. The first regions in at least one mode of operation of the device provide electrically parallel current paths extending through the body portion.
U.S. Pat. No. 6,818,513 to Marchant discloses a method of forming a superjunction trench gate field effect transistor device. FIG. 1A is a cross-sectional view of the superjunction trench gate field effect transistor device of Marchant. In the Marchant method a well region of a second conductivity type is formed in a semiconductor substrate 29 that has a major surface, an N− epitaxial portion 32 and a drain region 31 and is made of a first conductivity type, e.g., N-type. A source region 36 of the first conductivity type is formed in the well region and a trench gate electrode 43 is formed adjacent to the source region. A P− stripe trench 35 is formed extending from the major surface of the semiconductor substrate 29 into the semiconductor substrate to a predetermined depth. A semiconductor material of the second conductivity type, e.g., P-type, is deposited within the stripe trench 35. Each N+ source region 36 is adjacent to one of the gate structures 45 and is formed in a plurality of P− well regions 34, which are also formed in the semiconductor substrate 29. Each P− well region 34 is disposed adjacent to one of the gate structures 45. A contact 41 for the source regions 36 is present on the major surface 28 of the semiconductor substrate 29. The regions between the stripes 35 are quickly depleted of charge carriers as the depletion region 32 expands from the side-surfaces of adjacent stripes 35. FIG. 1B is cross-sectional view of another trench gate superjunction field effect transistor device of Marchant. As shown in this figure, the stripe 35 comprises a P− layer 35(a) and an inner dielectric material 35(b) that may be formed by oxidizing the P− layer 35(a) or a material such as silicon dioxide or air. However, the method of Marchant takes a lot of steps to etch and fill the stripe trench, which tends to increase the cost of devices that contain superjunction transistors made with the Marchant method. In addition, the stripe trench 35 is not self-aligned and the active cell pitch, i.e., from device trench to device trench, cannot be made smaller than about 12 μm to 16 μm.
It is within this context that embodiments of the present invention arise.